Our company successfully mass produced the first s

Our company has successfully mass produced the first small-size Mipi interface 2.0-inch LCD and 2.4-inch LCD, helping China's 5g construction and AI intelligent's technical requirements for LCD.
With the advent of 5g and AI intelligent era in China, the performance of CPU chip of hardware products has been greatly improved, and the requirements for LCD interface have also been improved. The demand for Mipi high-speed transmission interface is increasing. Mipi interface LCD screens have always been high-resolution screens of more than 3 inches. For small screens such as 2.0-inch LCD and 2.4-inch LCD, there are no Mipi interface products on the market. After a long time of research and development and increasing investment, our company has launched the first small-size 2.0-inch Mipi interface LCD and 2.4-inch Mipi interface LCD. IPS material is much better than the ready-made 2.0-inch LCD and 2.4-inch LCD on the market in terms of display effect, viewing angle and data transmission speed, so as to meet the needs of our customers for small-size Mipi interface LCD, The two products are now in mass production and supply with domestic and foreign customers.
Mipi is specially designed for power sensitive applications with low amplitude signal swing in high-speed (data transmission) mode. Figure 2 compares the signal swing of Mipi with other differential techniques.
Because Mipi is transmitted by differential signal, it needs to be designed strictly according to the general rules of differential design. The key is to realize the matching of differential impedance. Mipi protocol stipulates that the differential impedance of transmission line is 80-125 ohms.
Mipi is specially designed for power sensitive applications with low amplitude signal swing in high-speed (data transmission) mode. Figure 2 compares the signal swing of Mipi with other differential techniques.
Because Mipi is transmitted by differential signal, it needs to be designed strictly according to the general rules of differential design. The key is to realize the matching of differential impedance. Mipi protocol stipulates that the differential impedance of transmission line is 80-125 ohms.

Figure 2: comparison of signal amplitudes of several popular differential swing technologies

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Mipi specifies a differential clock channel (Lane) and a scalable number of data channels from 1 to 4, which can adjust the data rate according to the needs of processors and peripherals. Moreover, Mipi d-phy specification only gives the data rate range and does not specify the specific working rate. In an application, the available data channel and data rate are determined by the devices at both ends of the interface. However, the currently available Mipi d-phy IP core can provide a transmission rate of up to 1 Gbps per data channel, which undoubtedly means that Mipi is fully suitable for current and future high-performance applications.
There is another advantage of using Mipi as the data interface. Because Mipi DSI and csi-2 architecture bring flexibility to the new design and support remarkable functions such as XGA display and higher than 8 megapixel camera, Mipi is very suitable for new smart phone and mid design. With the bandwidth capability provided by the new processor design with Mipi function, it is now possible to consider using a single Mipi interface to realize novel functions such as high-resolution dual screen display and / or dual cameras.
In the design using these functions, high bandwidth analog switches designed and optimized for Mipi signals, such as fsa642 of Fairchild Semiconductor, can be used for switching between multiple display screens or camera components. Fsa642 is a high bandwidth three-way differential single pole double throw (SPDT) analog switch, which can share one Mipi clock channel and two Mipi data channels between two peripheral Mipi devices. Such a switch can provide some additional advantages: isolating stray signals (stubs) of unselected devices, and improving the flexibility of wiring and peripheral layout. In order to ensure the successful design of these physical switches on Mipi interconnection path, in addition to bandwidth, the following main switching parameters must be considered:
1. Turn off isolation: in order to maintain the signal integrity of the active clock / data path, the switch is required to have efficient turn off isolation performance. For high-speed Mipi differential signals with 200mV and maximum common mode mismatch of 5mv, the off isolation between switch paths should be - 30dBm or better.
2. Differential delay difference: the skew between the internal signals of the differential pair (differential internal delay difference) and the delay difference between the clock and the differential intersection of the data channel (inter channel delay difference) must be reduced to 50 PS or less. For these parameters, the industry's best delay difference performance of such switches is currently between 20 PS and 30 PS.
3. Switching impedance: when selecting analog switches, the third main consideration is the tradeoff between the impedance characteristics of on impedance (RON) and on capacitance (CON). Mipi d-phy link supports both low-power data transmission and high-speed data transmission modes. Therefore, the Ron of the switch should be balanced to optimize the performance of the mixed operating mode. Ideally, this parameter should be set separately for each operating mode. In the first mock exam, it is important to combine the best RON of each mode and maintain a very low switching CON to maintain the slew rate of the receiver. The general rule is that keeping con below 10 pf will help to avoid deterioration (extension) of the signal conversion time through the switch in high-speed mode.
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Compared with parallel port, Mipi interface module has the advantages of fast speed, large amount of data transmission, low power consumption and good anti-interference. It is more and more favored by customers and is growing rapidly. For example, for an 8m module with both Mipi and parallel port transmission, at least 11 transmission lines and up to 96m output clock are required for 8-bit parallel port transmission to achieve 12fps full pixel output; Using Mipi interface only needs 2 channels and 6 transmission lines to achieve the frame rate of 12fps under full pixels, and the consumed current will be about 20mA lower than that of parallel port transmission. Because Mipi is transmitted by differential signal, it needs to be designed strictly according to the general rules of differential design. The key is to realize the matching of differential impedance. Mipi protocol stipulates that the differential impedance of transmission line is 80-125 ohms.

The figure above is a typical ideal differential design state. In order to ensure the differential impedance, the line width and line distance should be carefully selected according to the software simulation; In order to give full play to the advantages of the differential line, the differential line pair should be closely coupled internally, the shape of the routing line should be symmetrical, and even the position of the vias should be placed symmetrically; The differential line needs to be of equal length to avoid bit error caused by transmission delay; In addition, it should be noted that in order to achieve close coupling, there should be no ground wire in the middle of the differential pair. In the definition of pin, it is best to avoid placing the grounding pad between the differential pairs (referring to two adjacent differential lines physically).
The channel mode and line level of Mipi are briefly introduced below. In normal operation mode, the data channel is in high-speed mode or control mode. In the high-speed mode, the channel state is differential 0 or 1, that is, when p is higher than N in the line pair, it is defined as 1, and when p is lower than N, it is defined as 0. At this time, the typical online voltage is differential 200mV. Please note that the image signal is transmitted only in the high-speed mode; In the control mode, the typical amplitude of high level is 1.2V. At this time, the signals on P and N are not differential signals, but independent of each other. When p is 1.2V and N is also 1.2V, Mipi protocol defines the state as LP11. Similarly, when p is 1.2V and N is 0V, Mipi protocol defines the state as LP10, and so on. In the control mode, LP11, LP10, LP01 and lp00 can be composed of four different states; Mipi protocol stipulates that the different timing composed of four different states of the control mode represents the entry or exit of the high-speed mode, etc; For example, after lp11-lp01-lp00 sequence, enter the high-speed mode. The figure below is an illustration of the on-line level.